Circuits which receive and store an input voltage are commonly referred to as sample-and-hold circuits. Many of these types of circuits have a nonvalid period of operation when an input voltage is being sampled and stored and a valid period of operation when the most recently sampled value is outputted. A disadvantage with this type of circuit operation is that many applications require an output voltage to be constantly present. Since input voltages are sampled and held by charge storage devices, most sample-and-hold circuits utilize capacitors in conjunction with transistor amplifiers as shown in U.S. Pat. No. 4,542,304 entitled "Switched Capacitor Feedback Sample-and-Hold Circuit" by Eric Swanson and U.S. Pat. No. 4,585,956 also entitled "Switched Capacitor Feedback Sample-and-Hold Circuit" by Hans Lie. In each of these teachings, a constant output voltage is provided which is commonly referred to as a one hundred percent duty cycle output. However, previous sample-and-hold circuits have had offset voltage and/or switch feedthru errors associated with the output voltage. Error voltages resulting from inherent offset voltage of a differential amplifier distort the accuracy of an output voltage sample. Previous sample-and-hold circuits typically also have an undesirably long sample period which unnecessarily commits circuitry providing the sampled voltage to maintain the sample. Other disadvantages with known sample-and-hold circuits include unsatisfactory power supply rejection (PSR) performance.